RTL Complete · 13/13 Tests Passing · FPGA Bringup Active

The Edge AI Chip
Signal Processing Built In

32.8 TOPS INT8 · 512 GFLOPS FP16 · Native FFT / DCT / STFT / Wavelet
GF 22FDX · 2.5W · OEM Silicon IP

0TOPSINT8 Compute
0GFLOPSFP16 Compute
0UnitsSignal Engine
2.5WTypical Power
INT8 COMPUTE ENGINE 32.8 TOPS @ 2GHz · GF 22FDX SIGNAL ENGINE 64 DSP Units FFT·DCT·STFT·Wave FP16 COMPUTE ENGINE 512 GFLOPS Full IEEE 754 precision SPARSITY ENGINE Unstructured ~40% uplift ON-CHIP SRAM 32 MB MAC output buffer eMRAM STORE 32 MB Model weight NVM AXI4 FABRIC I/O RING · AXI4 · APB · GPIO MOSIMISO CLKD[0] D[1]D[7] A[0]A[7] A[15]VDD GNDVIO AXI_WRAXI_RD INTFFT_IN FFT_OUTTRIG MAC_ENCLR VALIDAVDD AGNDVREF RST SYS_CLK PLL_REF JTAG_TDI JTAG_TDO JTAG_TCK I2C_SCL I2C_SDA UART_TX VDD_CORE GND VDD_IO AdaptCore V5.4 · GF22FDX · © 2026
GF 22FDX · 22nm FD-SOI
AdaptCore V5.4 · QFP-128

Every Block Built for Edge AI

No signal transform tax. No off-chip memory bottleneck. No ecosystem lock-in.

INT8 Compute Engine

32.8 TOPS

Proprietary MAC architecture with unstructured sparsity engine. ~40% effective throughput uplift on sparse models.

@ 2 GHz · GF 22FDX · Undisclosed topology

64-Unit Signal Engine

Native DSP

FFT · DCT · STFT · Wavelet — all first-class silicon. No CPU offload. No latency penalty.

Cooley-Tukey DIF · Q8.8 Fixed Point

FP16 Compute Engine

512 GFLOPS

Half-precision inference engine. Handles mixed INT8/FP16 pipelines natively — ideal for transformer and vision models.

IEEE 754 · Half Precision · Undisclosed topology

64 MB On-Chip Memory

DRAM-Free

32 MB SRAM (MAC output) + 32 MB eMRAM (model weights). Entire MobileNet V2 fits on-chip.

Non-volatile weights · Zero reload latency

Unstructured Sparsity

~40% Uplift

Skip zero MACs at hardware level — no software pruning required. Works with any model out of the box.

Dynamic · Model-agnostic

AXI4 Fabric

OEM-Ready

Standard AXI4 + AXI4-Lite + APB interfaces. Drops into any SoC without custom glue logic.

AMBA compliant · Full register map
ONNX AC graph → schedule → codegen → binary

AdaptCore Compiler SDK In Development

ONNX / PyTorch → Native Binary

End-to-end compiler toolchain that maps standard neural network graphs directly to AdaptCore's proprietary compute engine — no manual kernel writing required.

📥
Import
ONNX · PyTorch
TFLite · Custom
🔍
Graph IR
Op fusion
Constant folding
📐
Scheduler
MAC tiling
Signal offload
Codegen
INT8 / FP16
Sparsity aware
Binary
AC native
executable
RTL Complete — Verilog V5.4
13/13 Testcases Passing
FPGA Bringup — Azure NP10s
Compiler Toolchain — In Development
Tapeout — Feb 2027
First Silicon — Jun 2027

We Beat Every Comp at Our Power Envelope

ChipINT8 TOPSFP16 SparsitySignal TransformsPower
AdaptCoreOUR IP 32.8512 GFLOPS Unstructured FFT · DCT · STFT · Wavelet 2.5W
Google Edge TPU42W
Hailo-8262.5W
Apple ANE (A17)35FP16 (locked)~5W
NVIDIA Jetson Orin NX501.6 TFLOPSStruct 2:410–25W
Qualcomm Hexagon 8G3~455–8W

✗ = not supported at this power point · Figures at typical inference workload

One Chip. Four Markets.

Native signal processing unlocks applications no competitor can match at this power.

01

Smart Camera / Vision SOMs

Industrial inspection, surveillance, robotics. INT8 MAC array delivers 32.8 TOPS for real-time multi-stream object detection and segmentation — all under 3W.

  • Multi-stream HD inference (4× 1080p simultaneously)
  • On-chip SRAM eliminates external DRAM for small models
  • Unstructured sparsity: pruned YOLOv8 at near-lossless accuracy
  • AXI4-Stream camera interface — zero glue logic
Engine: INT8 MACs · Sparsity · eMRAM
02

Telecom Baseband Offload

5G RAN and radar signal processing. Native 64-unit FFT engine computes full OFDM demodulation in silicon — no separate DSP co-processor required.

  • 5G NR OFDM: 4096-point FFT in hardware
  • Radar: Range-Doppler FFT2D natively
  • Channel estimation via STFT — real-time
  • 60% lower power vs CPU-offload baseline
Engine: 64-Unit FFT · STFT · Signal Engine
03

Medical Imaging

MRI reconstruction, CT filtering, ultrasound AI. Wavelet and DCT engines handle imaging transforms natively — eliminating the reconstruction CPU entirely in portable devices.

  • MRI: k-space → image via 2D FFT in silicon
  • CT: Filtered back-projection via DCT engine
  • Ultrasound: Wavelet denoising on-chip
  • FP16 engine for diagnostic-quality precision
Engine: Wavelet · DCT · FP16 · Signal Engine
04

Audio AI / Speech

Always-on ASR, noise cancellation, voice activity detection. STFT-native acceleration processes audio features in silicon — enabling continuous listening at under 500mW.

  • STFT feature extraction at <500mW
  • On-device Whisper-tiny / Wav2Vec2
  • Real-time noise cancellation (beamforming + INT8)
  • Wake-word + full ASR pipeline on single chip
Engine: STFT · INT8 MACs · Always-On

License AdaptCore for Your SoC

IEEE P1735 encrypted delivery. Zero RTL exposure. Three tiers to match your programme.

Tier 1

Firm IP

IEEE 1735 Encrypted Netlist
Pricing on Request
Licence fee + per-unit royalty — negotiated per programme
  • IEEE P1735 encrypted gate netlist
  • Cadence · Synopsys · Siemens tools
  • Behavioural model for Verilator
  • Full UVM testbench
  • 90-day integration support
  • No GDS / layout
  • Customer synthesizes to own node
Best for: Startups · Multi-node flexibility
Enquire
Tier 3

NRE + Licence

Custom Integration Engineering
Pricing on Request
NRE + IP licence — scoped to programme requirements
  • Everything in Tier 1 or Tier 2
  • Custom AXI / APB / proprietary interface
  • Power domain partitioning
  • Custom memory configuration
  • FPGA prototype delivery
  • Full tapeout support
  • IP ownership retained by AdaptCore
Best for: Defence · Medical · Telecom OEMs
Discuss Scope
Every licence is negotiated — common customisations we accommodate:
🔧
Interface swap Replace AXI4 with APB, AHB, or your proprietary on-chip bus
💾
Memory resize Scale SRAM / eMRAM up or down to fit your die budget
Clock / voltage domain Multi-VDD partitioning, custom clock tree for your power island
📐
Floorplan constraints Aspect ratio, keep-out zones, pin placement for your P&R flow
🔩
Signal engine subset Enable only the transforms you need — FFT-only, STFT-only, etc.
🏭
Process node retarget Firm IP re-synthesised to your foundry and node (TSMC, Samsung, GF)
Zero source exposure — guaranteed. All tiers delivered via IEEE P1735 encryption. Your evaluation team can simulate and synthesize the IP using Cadence Xcelium, Synopsys VCS, or Siemens Questa. The Verilog RTL is never shared under any circumstance or tier.

Start the Conversation

Share your use case — datasheet + integration guide within 48 hours.

IP Availability
Firm IP — Now
Hard IP (GDS) — Q2 2027
NDA Policy
Mutual NDA before any technical disclosure. RTL never shared.
Process
GF 22FDX (Hard IP)
Node-agnostic (Firm IP)